1. Field of the Invention
The present invention relates to the field of communication systems including communication among computer systems that are networked together. More specifically, the present invention relates to computer controlled communication systems having improved message queuing mechanisms for use with a network interface card (NIC).
2. Related Art
Networked communication systems (xe2x80x9cnetworksxe2x80x9d) are very popular mechanisms for allowing multiple computers and peripheral systems to communicate with each other within larger computer systems. Local area networks (LANs) are one type of networked communication system and one type of LAN utilizes the Ethernet communication standard (IEEE 802.3). One Ethernet LAN standard is the 10 Base T system which communicates at a rate of 10 Megabits per second and another Ethernet LAN standard, 100 Base T, communicates at a rate of 100 Megabits per second. Computer systems can also communicate with coupled peripherals using different bus standards including the Peripheral Component Interconnect (PCI) bus standard and the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) bus standards. The IEEE 1394 serial communication standard is also another popular bus standard adopted by manufacturers of computer systems and peripheral components for its high speed and interconnection flexibilities.
FIG. 1A illustrates a prior art computer system 10 that can communicate data packets (messages) to and from a network of computers and peripherals 20 (a xe2x80x9cnetworkxe2x80x9d). System 10 contains a processor 30 interfaced with a peripheral components interconnect (PCI) bus 25 which is also interfaced with a NIC device 12 and a volatile memory unit 40. The NIC 12 provides communication with the network 20. The NIC 12 provides a single register, called the Tx entry point 14, for queuing up data packets for transmission onto the network 20. The Tx entry point 14 contains a pointer to a linked list of data packets 45a-45n that reside in the volatile memory unit 40. Each data packet in the linked list contains a pointer 42a-42c to the next data packet for transmission. The NIC 12 reads the data packets of the linked list, in order, from the memory unit 40 and transmits then to network 20. When all the data packets in the linked list have been transmitted, or when the network 20 is down, the NIC 12 stops processing the data that is indicated by the pointer of the Tx entry point 14.
FIG. 1B illustrates a flow diagram 60 of steps performed by the processor 30 of system 10 (FIG. 1a) for queuing up a new data packet to NIC 12 for transmission over network 20. This flow diagram 60 illustrates the latencies attributed to system 10 for queuing up a new data packet. These latencies decrease the overall throughput of PCI bus 25 and degrade the performance of NIC 12 thereby decreasing the quality of service of system 10. At step 62 of FIG. 1B, to queue up a data packet for transmission, the processor 30 constructs the new data packet in a vacant memory space of memory unit 40. At step 64, the processor 30 requests access to the PCI bus 25, waits its turn in the round-robin arbitration scheme for the access grant, and then commands the NIC 12 to stall its current activity. Each of these activities of step 64 introduces unwanted latencies. At step 66, while the NIC 12 remains stalled, the processor 30 again requests PCI bus access, waits for the grant, and then sorts through the linked list of data packets 45a-45n to determine the last data packet in the list. The new data packet is then appended (e.g., linked) to the last data packet, 45n. Each of these activities of step 66 introduces more unwanted latencies. Lastly, at step 68, while the NIC remains stalled, the processor 30 again requests PCI bus access, waits for the grant, and then signals the NIC 12 to resume its activities. Again, each of these activities of step 68 introduces unwanted latencies.
As shown above, the process 60 of queuing the new data packet for transmission requires at least 3 PCI bus requests which introduce unwanted latency because each request is followed by a waiting period for the bus grant and to make matters worse, the first PCI bus request stalls the NIC 12. The NIC 12 is stalled because it operates independently from the processor 30, sending and receiving information based on the data""s availability and the network""s throughput. In other words, at the time the processor 30 wants to append the new data packet to the linked list, the processor 30 does not know which data packet in the linked list that the NIC 12 is processing. Assuming the NIC is not stalled, if the processor 30 appends the new data packet to the linked list just after the NIC 12 processed the last part of the last data packet 45n, then the newly appended data packet would never be recognized by the NIC 12 and thereby would never be transmitted to network 20. This is called a xe2x80x9cracexe2x80x9d condition because the processor 30 and the NIC 12 are not synchronized and the processor 30 does not know the transmission status of the NIC 12 at all times. Therefore, to eliminate the race condition, the processor 30 stalls the NIC 12, appends the new data packet to the linked list, and then allows the NIC 12 to resume its activities as shown in FIG. 1B.
Unfortunately, requesting PCI bus access and NIC stalling, in accordance with the steps 60 of FIG. 1B, heavily degrade system performance. Each PCI bus request generated by the processor 30 interrupts and degrades the communication of other components on the PCI bus 25. Furthermore, while the processor 30 waits for PCI bus access in order to link the new packet to the linked list, the NIC 12 remains stalled, again degrading communication performance.
Moreover, in many new processing environments and architectures, communication systems and computer systems need to process and communicate data packets of different data types. For instance, electronic mail (email) messages are sent and received by the system 10 (FIG. 1A). Also, voice and image data are sent and received by the system 10 as well as other multi-media content. However, live broadcasts (e.g., voice and data) need high priority transmission without jitter to allow natural conversation and appearance, while other information, such as email messages, can be communicated successfully at lower priorities. Unfortunately, system 10 does not provide any special communication techniques for messages of different priorities.
Accordingly, what is needed is a communication system that reduces the latencies described above for queuing a new data packet for transmission by a NIC. What is needed further is a communication system that provides mechanisms for handling messages (data packets) having different priorities. The present invention provides these advantageous features. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
A first-in-first-out (FIFO) entry point for a network interface card is described herein. The novel circuit of the present invention provides a FIFO implementation of a entry point of a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the NIC for the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point register thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network. If the packet points to a next packet, then that next packet is sent, otherwise the next-in-line pointer of the Tx FIFO entry point is then processed by the NIC. Signals indicate when the Rx or Tx FIFO entry point circuits are full. An analogous process operates for the Rx FIFO entry point. Providing a queued entry point reduces processor utilization and peripheral component interconnect (PCI) bus utilization in communicating packets with the network because memory pointers can be directly pushed onto the transmit FIFO by the processor without encountering race conditions. Therefore, providing a queued entry point increases NIC efficiency because the NIC does not require stalling and unstalling to queue a data packet. Moreover, the processor can directly load the new pointer into the FIFO entry point circuit and does not need to search through a linked list to append the new data packet to its end. Both act to improve quality of service performance.
A scaleable priority arbiter is also described herein for arbitrating between multiple first-in-first-out (FIFO) entry point circuits of a NIC. The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority 1, priority 2, . . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer. The multiplexer selects between two inputs, a first input is dedicated to data packets of the priority type corresponding to the circuit stage and the other input comes from the lower priority chain. In one embodiment, timers regulate the transmission of isochronous packets. The arbiter transmits the isochronous packet, if any, with the timer and otherwise allows the next stage a transmit turn. The next stage checks if a priority 1 packet is present and if a priority 1 packet was not sent the last time its turn was reached. If yes, the priority 1 packet is sent, if not, then the above decision is repeated with respect to the next lower priority circuit stage. Priority arbitration improves quality of service performance and reduces host processor utilization.
Specifically, embodiments of the present invention include a network adapter card (NIC) for coupling with a computer system having a processor and a memory unit, the NIC comprising: a queued transmit entry point circuit comprising a transmit entry point register and a plurality of memory cells configured as a first-in-first-out (FIFO) memory circuit, the transmit entry point register for receiving new data packet pointers from the processor and for queuing the new data packet pointers into the FIFO memory circuit, the transmit entry point register for maintaining the oldest queued data packet pointer of the queued transmit entry point circuit; a transmit FIFO memory circuit for containing digital data to be transmitted onto a network; and a control circuit for accessing digital data from a memory space of the memory unit of the computer system and for supplying the digital data to the transmit FIFO memory circuit, the memory space being identified by the oldest queued data packet pointer as maintained by the transmit entry point register.
Embodiments include the above circuit and wherein the transmit entry point register is the only memory cell of the queued transmit entry point circuit that is visible to the processor and wherein the queued transmit entry point circuit supplies the control circuit with a next-in-order data packet pointer upon completion of the most recently transmitted data packet.
Embodiments further include the above circuit and further comprising: a receive FIFO memory circuit for receiving digital data from the network; and a queued receive entry point circuit comprising a receive entry point register and a plurality of memory cells configured as a FIFO memory circuit, the receive entry point register for receiving new memory space pointers and for queuing the new memory space pointers into the FIFO memory circuit of the queued receive entry point circuit, the receive entry point register for maintaining the oldest queued memory space pointer of the queued receive entry point circuit; and wherein the control circuit is also for storing digital data from the receive FIFO memory circuit to the memory unit of the computer system at a memory space indicated by the memory space pointer maintained by the FIFO receive entry point register.